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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with hold timing violation

Hi all, I always a have a "timing not met" critical warning when compiling a VHDL module. I think the problem is restricted to this part of code, since the involved signal appears only here. ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Yes. Having a create_clock assignment on a register basically means that clock "just appears" there. It's edge starts there at time 0. The clock for clk also starts at time 0, but has a long delay to rx_clk, and hence the large clock skew causes a hold violation. Making a generated clock that works is the best method. (And I never enter constraints in the console. Always put them in the .sdc. If you want to enter them via the GUI, open the .sdc in Quartus and go to Edit -> Insert Constraint).

Now that the generated clock is correct, the delay to clock rx_clk is accounted for, the skew goes away, and it meets timing.