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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem with changing pin assignments

Hi, I almost finished my FPGA & board design . I wanted to add the possibilities to use CRC error check and dev_clr. the pins dedicated for those functions are already being used for othe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Sometimes the pin planner operation is a bit arbitrary. I don't know what's exactly going on in your design but you usually have unlimited control in the assignment editor. You can also temporarily remove the said pin from the top entity port.

It's possibly annoying, but a trivial issue, though.