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I think you should use "vector" signals instead of sign or unsign.
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A signed/usnigned is a vector type. and is perfectly suitable here.
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I do not write: met <= met + 25 because I want to increase the variable 'met' step by step.
Specifically I want 'met' to take the values 1 then 2 then 3 and etc and this is the reason that I use the the loop in my code.
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Then you would not use a for loop. loops unrol into parrallel logic. You need a clock. And a good VHDL tutorial (I think you need to go back to step one and start again. Writing VHDL is NOT like writing C)
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