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Altera_Forum
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12 years ago

problem with an addition in a vhdl code

Hello, I have written the following code but I do not take the right results from the addition: met <=met+monada; I think that the problem is that I have the signal met twice. Specifically...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes I know that here the variable met is defined as signed.

I thought that if I do not initialize a variable then it is equal to 0.

According to Tricky it did not increased because met is a signal.

What should I do so as to be increased?In which type should I define it?