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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem with an addition in a vhdl code

Hello, I have written the following code but I do not take the right results from the addition: met <=met+monada; I think that the problem is that I have the signal met twice. Specifically...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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and then to be increased so as finally to be equal to 25.

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No, it's not initialized to 0, and not counting up, as Tricky explained.

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This is a simple code that I tried to do because I try to write a code and there the variable 'met' is a fixed point number and I added it with a fixed point number.

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It's defined as signed, not fixed point.

You should also get rid of conflicting libraries.