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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem with an addition in a vhdl code

Hello, I have written the following code but I do not take the right results from the addition: met <=met+monada; I think that the problem is that I have the signal met twice. Specifically...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Sorry I made a mistake when I reported the line.

The line that I wanted to refer is this:met <=met+1;

With this code I wanted to do the addition operation. I wanted the variable 'met' to be zero when we insert in the loop

FOR i IN 1 TO 25 LOOP

met <=met+1;

END LOOP;

and then to be increased so as finally to be equal to 25.

This is a simple code that I tried to do because I try to write a code and there the variable 'met' is a fixed point number and I added it with a fixed point number.