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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem with an addition in a vhdl code

Hello, I have written the following code but I do not take the right results from the addition: met <=met+monada; I think that the problem is that I have the signal met twice. Specifically...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The line reported to cause problems can't be found in the code.

Presently, the code sets an output value nn according to input z. But signal met isn't initialized in the process, so the output will be undefined.