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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem with an addition in a vhdl code

Hello, I have written the following code but I do not take the right results from the addition: met <=met+monada; I think that the problem is that I have the signal met twice. Specifically...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I dont know which line you're talking about has an error, because you dont point it out.

But I suspect the initial problem comes from your for loop. A signal is only assigned when a process suspends. So in your code, met <= met + 1; occurs 25 times, but as the signal wont be updated, it is just a single + 1, not 25x +1.

So can you please rephrase your question, with the problem marked in your code.