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Altera_Forum's avatar
Altera_Forum
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12 years ago

Problem with 7 segment display

Hello to everyone,

I've got a problem with 7 segment display on my Altera DE1 board. I want to do the same thing:

With 5 switch i wanto to set a binary number for example: SW1-SW2-SW3-SW4-SW5 are in ON Position the number is "11111" that in decimal is 31 and want to see 31 on the 7 segment display.

At the beginning i've create a std_logic_vector with this declaration and initialization:

signal First std_logic_vector (0 to 4); ----- declaration

First <= (x4,x3,x2,x1,x0); ----- initialization

Then i think that it's necessary convert the number that is inside on the vector to a decimal number but according me there is a problem, if i convert it the number (for example 31) will be avaiable on the first position of the another vector, but my idea is not this, i want that every number have a different position, i explain better

Vector 1

Position0: contain number 1

Position1: contain number 3

so i will match every number with the following algorithm for visualize the number on 7 segment display

function int_to7seg (a: std_logic_vector) return std_logic_vector

variable result: std_logic_vector (6 downto 0);

begin

casa a is:

when 0 => result:="1000000";

.................

end case;

return result;

end int_to7seg;

There is anyone that can help me?

Thanks a lot for your cooperation

Best Regards

Michele

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Michele,

    I wrote a simple top-level design for the DE1 and posted in this thread:

    http://www.alteraforum.com/forum/showthread.php?t=35687

    Download de1_basic.zip, unzip it, (delete the qwork folder), and follow the instructions in the readme.txt file. Then look at the VHDL code.

    Try to change the code so that the switches control one of the 7-segment displays ... start with displaying hexadecimal, and then move onto BCD (which is what your question above indicates you want).

    I'd tell you how, but then you would not learn, so see if you can figure out what to do, and if you have trouble, post a question.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    ok dave, i've just finished the program to control with 7 segment display and switch hexadecimal, the only answer that i want (if is possible) is that:

    i can insert into a vector an integer number in two different position? for example number 31 ---> 1 into index 0 and 3 into index 1

    Cheers

    Michele
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    the only answer that i want (if is possible) is that:

    i can insert into a vector an integer number in two different position? for example number 31 ---> 1 into index 0 and 3 into index 1

    --- Quote End ---

    Try this: 

    
signal bcd : std_logic_vector(7 downto 0) := X"31";
signal hex_a_data : std_logic_vector(3 downto 0);
signal hex_b_data : std_logic_vector(3 downto 0);
-- Split the BCD value into two 4-bit values
hex_a_data <= bcd(3 downto 0);
hex_b_data <= bcd(7 downto 4);

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    ok now i try. Can i post it at the moment the code that i have produce for see if according you is correct?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    This is the first part: 

    
library ieee; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
use work.VISDIS3.all;
entity FunzioneP13 is
	port (
			SW: in STD_LOGIC_VECTOR (9 downto 0);
			HEX0: out STD_LOGIC_VECTOR (0 to 6);
			HEX1: out STD_LOGIC_VECTOR (0 to 6);
			HEX2: out STD_LOGIC_VECTOR (0 to 6);
			HEX3: out STD_LOGIC_VECTOR (0 to 6)
			);
end FunzioneP13;
architecture Behavior of FunzioneP13 is
signal x0: std_logic;
signal x1: std_logic;
signal x2: std_logic;
signal x3: std_logic;
signal x4: std_logic;
signal first: std_logic_vector(0 to 4);
signal temp: integer;
begin
	x0<= SW(9);
	x1<= SW(8);
	x2<= SW(7);
	x3<= SW(6);
	x4<= SW(5);
PROCESS(X0,X1,X2,X3,X4)
BEGIN
for i in 0 to 4 loop
	first(i)<=SW(I);
END LOOP;
	temp<=VEC_TOINT(first);
	HEX0<=INT_TO7SEG(temp);
END PROCESS;
end architecture;

    And this is the package 

    
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
PACKAGE VISDIS3 IS
    FUNCTION INT_TO7SEG (A:INTEGER) RETURN STD_LOGIC_VECTOR;
    FUNCTION VEC_TOINT  (A: in STD_LOGIC_VECTOR) RETURN INTEGER;
END VISDIS3;
PACKAGE BODY VISDIS3 IS
	FUNCTION INT_TO7SEG (A:INTEGER) RETURN STD_LOGIC_VECTOR IS
	VARIABLE RESULT: STD_LOGIC_VECTOR(6 downto 0);
	BEGIN
	CASE A IS
	  WHEN 0 => RESULT:="0000001";
	  WHEN 1 => RESULT:="1111001";
	  WHEN 2 => RESULT:="0100100";
	  WHEN 3 => RESULT:="0110000";
	  WHEN 4 => RESULT:="0011001";
	  WHEN 5 => RESULT:="0010010";
	  WHEN 6 => RESULT:="0000010";
	  WHEN 7 => RESULT:="1111000";
	  WHEN 8 => RESULT:="0000000";
	  WHEN 9 => RESULT:="0010000";
	  WHEN OTHERS => RESULT:=(OTHERS=>'0');
	END CASE;
	RETURN RESULT;
	END INT_TO7SEG;
   --------------------------------------------------
	FUNCTION VEC_TOINT (A: in STD_LOGIC_VECTOR) RETURN INTEGER IS
	variable temp: bit_vector(A'range);
	variable result: integer :=0;
	BEGIN
		for index in A'range loop
			result :=result * 2 + bit'pos(temp(index));
		end loop;
		if A(A'left) = '1' then
			result :=(-result)-1;
		end if;
		return result;	
	END VEC_TOINT;
   ---------------------------------------------------
END VISDIS3;
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Here's a few comments on your code;

    1. Incorrect use of libraries 

    
library ieee; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;

    You need to learn what VHDL packages are used for, and not "randomly" add packages to your design. In this case here you have added conflicting packages to your design. In general if using signed, unsigned, and real types you would use the packages: 

    
library ieee; 
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;

    The packages I removed are non-standard, and are not recommended in VHDL code. Since your code does not use signed, unsigned, or real, you could also remove the last two packages in this list.

    2. Invalid process construct 

    
PROCESS(X0,X1,X2,X3,X4)
BEGIN
for i in 0 to 4 loop
    first(i)<=SW(I);
END LOOP;
    temp<=VEC_TOINT(first);
    HEX0<=INT_TO7SEG(temp);
END PROCESS;

    Did you even try to compile this code?

    A combinatorial process should list the signals it is sensitive to; why do you list X0,X1,X2,X3,X4 which are not even used, and not list SW which is used?

    Please don't waste the time of the readers of this forum. Try and compile your code using Quartus and Modelsim first, and read the error messages these tools will produce.

    Cheers,

    Dave