Problem with 7 segment display

Here's a few comments on your code;

1. Incorrect use of libraries

library ieee; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;

You need to learn what VHDL packages are used for, and not "randomly" add packages to your design. In this case here you have added conflicting packages to your design. In general if using signed, unsigned, and real types you would use the packages:

library ieee; 
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;

The packages I removed are non-standard, and are not recommended in VHDL code. Since your code does not use signed, unsigned, or real, you could also remove the last two packages in this list.

2. Invalid process construct

PROCESS(X0,X1,X2,X3,X4)
BEGIN
for i in 0 to 4 loop
    first(i)<=SW(I);
END LOOP;
    temp<=VEC_TOINT(first);
    HEX0<=INT_TO7SEG(temp);
END PROCESS;

Did you even try to compile this code?

A combinatorial process should list the signals it is sensitive to; why do you list X0,X1,X2,X3,X4 which are not even used, and not list SW which is used?

Please don't waste the time of the readers of this forum. Try and compile your code using Quartus and Modelsim first, and read the error messages these tools will produce.

Cheers,

Dave