Honored Contributor
Occasional ContributorI have same error on Quartus 25.1
Error: pcie_ed.custom_cntrlr_0.avalon_slave: Agent with readdatavalid signal must support at least 1 pending read.
as per https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/interface-properties.html
I tried setting "maximumPendingReadTransactions " parameter by platform designer > IP> Edit IP> Parameters> add parameter
it didnt work and I cant generate HDL due to this error Pls help
Super ContributorProbably would be better to create a new thread instead of reopening one from 13 years ago.
In any case, how are you coding the signal in your custom component? And you must be using pipelined transfers with variable latency: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/pipelined-read-transfer-with-variable.html
