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ASuba's avatar
ASuba
Icon for New Contributor rankNew Contributor
7 years ago

Problem while simulating system design with DDR3 memory controller

Hi I have recently started working with Nios11 based System design using Quartus for a project. I created the system in Platform Designer (qsys) and exported it to Nios SBT for writing simple code ...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Please Refer example and below link to debug.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-simulating-niosii.html

http://ebook.pldworld.com/_Semiconductors/ALTERA/one_click_niosII_docs_9_0/files/an351.pdf

DDR3 example.

https://fpgawiki.intel.com/wiki/Design_Example_-_Basic_DDR3_UniPHY_bring_up

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)