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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem when synthesizing top module with quartus II

I just start to build my first project using this software. The top module has a function of counting pulse to 100 and then return to 0. To simplify it, I use two decimal counter named decimal to build it, 

decimal m1(clk,en,ret,data,cout_mid),m2(cout_mid,en,ret,data,cout);
but the top module fails when synthesized. Errors listed below: 

Error (10228): Verilog HDL error at decimal.v(1): module "decimal" cannot be declared more than once
It’s really weird, can somebody help me? Thank u

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think, the error is in the design files overall strcuture, not shown in your post. I suggest to start with Verilog designs from the Quartus design templates to avoid simple syntax errors.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The error like this could appear if you add to your project two or more files that have inside description of decimal.v module.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    thank u both, I have solved this problem. Using this software, there is no need to include the bottom module file, which will be recognized automatically.