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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem when synthesizing top module with quartus II

I just start to build my first project using this software. The top module has a function of counting pulse to 100 and then return to 0. To simplify it, I use two decimal counter named decimal to bui...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I think, the error is in the design files overall strcuture, not shown in your post. I suggest to start with Verilog designs from the Quartus design templates to avoid simple syntax errors.