Problem when compiling project in Quartus 13.0

Normally to help routability, the best thing to do is turn up the placement effort(assignments -> settings -> fitter -> More -> Placement Effort -> 4). A better placement also means less routing congestion and more likely to get a route. That's for the "generic" case though. In your case the two signals are control signals, and more importantly, have ~CLKENA0 appended to them. This is done when it goes through an altclkctrl block, which is how it gets onto a global signal(or regional/dual-regional, etc.). So it seems like you're running out of the underlying clock routing resources, which is not good. What device is this?

It's hard to diagnose more, but two thoughts:

1) Take the reset_synchronizer signal off a global. Just do:

set_instance_assignment -name GLOBAL_SIGNAL "OFF" -to blaa

and replace blaa with the full signal name for the ...altera_reset_synchronizer..., but without the ~CLKENA0 at the end. (I can't cut and paste from your sceen-shot).

2) Go to Global section and see if there are any other signals you can take off globals.

I'm not positive this is the issue, but taking a guess...