Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Problem simulating transceiver megacore Nativelink

I am new to Altera Megacores and am having trouble simulating a VHDL project using Altera Megacores in the web edition of Quartus/ Modelsim-Altera. I am trying to use Nativelink so I do not have to g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks very much for your reply Joe.

I found my problem was due to choosing VHDL for the output EDA netlist setting in Quartus Nativelink set up. When I set to Verilog HDL it all works fine. At least it simulates. Now I have to make it work.

I only just started looking at transceivers and it is the first time I have used the MegaCores. I wasn't sure if the problems I was having were due to my design or with the tools.

I will have a look through your archive and learn from your hard work.

Thanks again.

Phil