Problem simulating transceiver megacore Nativelink

Hello, I just did a small design with the Cyclone V Transceiver Native IP Core. Please take a look at my attachments. I archived my project open it up and look at my .bdf file to see how I connected up the transceiver, the reset module and the configuration module. In an not using any protocol. I'm only use the Gbe Protocol-Ordered Sets and Special code (IDL1 and Carrier Extend) to implement a simple link to another transceiver on another board, see page 4-17 in the Cyclone V Device Handbook Volume 2. I'm also using the tx_datak[] and rx_datak[] port to put the link in Control mode or Data mode. Please take a look at my testbench in the testbench directory. I only did an Function Simulation because the RTL simulation would not work. In my attached design I use a testbench to send data to the transceiver and in the testbench I connect the rx_serial_data port to the tx_serial_data port. I first send and IDLE code then a Carrier Code and then real data.