Altera_ForumHonored Contributor16 years agoProblem rebuilding source with new Quartus II Hello, I recently inherited a project board which has a Stratix II EP2S30F672 FPGA which is booted from an EPC4QC100. Project originally compiled under quartus vers 7. Now when the project is co...Show More
Altera_ForumHonored Contributor16 years agoHave you tried JTAGing the .sof file directly to the fpga?
Recent Discussionsrecovery timing issueerror in JTAG server (error code 35) and autodetect (unable to scan device chain) Quartus 18.1Quartus/Signaltap complains about wrong versionLicense issueNo access to the Self Service Licensing Center (SSLC)