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Of course the disadvantage of not using a PLL is that you lose the ability to balance your setup and hold slack by adjusting the clock offset.
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If you also drive the data out using ALTDDIO_OUT blocks (connecting the same signal to both the HI and LO data input) then with the proposed inverted clock output your set-up and hold time will be well close to 1/2 clock period and thus quite well balanced.
But at 50MHz even without ALTDDIO_OUT for the data and with the inverted clock output you will get plenty set-up and hold time if you can make sure that the output data is registered in the IO-cell (by setting Fast Output Register in the Assignment Editor).
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