problem on set_output_delay

And there's a big problem!

I haven't used Altera's Device before. After synthesis, I know that PLL can only be fed by external input clock. So I guess using a PLL to do the phase shift isn't practical because I didn't connect any IO to PLL dedicate inputs (I think they are CLK0~CLK3).

Directly output the data clock seems a way, then it all depends on the fitting to ensure the setup and hold timing meet DSP's needs.

Can any effort be made to save this design ?

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My way is to connect input clock to an LPM_INV to generate 180 degree phase shift output clock. The register to output setup and hold slacks are still the same as using PLL to do the 180 degree phase shift. So it all goes back to the second thread ----- How to improve the timing margin?