problem on set_output_delay

There's something I missed to mention ---- I use SDR to transfer the output to DSP, and I use a PLL to generate the output clock and data clock. All the manuals on set_output_delay constraint suggest shift the output clock by 90 degree when using DDR.

I shifted the output clock by 180 degree, then the IO timing errors vanished. However, the setup slack is 0.28 ns, and the hold slack is 1.72 ns. What else can I do to improve the margin?

What goes worse is clock hold slack has errors. There's the description of the problem:

In module1, PLL1 generates clk1;

In module2, clk1 feeds PLL2 to generate clk2, and clk2 generates fifo_address_read signal;

clk1 and clk2 are phase aligned;

In module3, which constains module 1 and module 2, clk1 and fifo_address_read feed the FIFO instance's read clock pin and read address pin.

The error indicates the path between launch clock clk2 and latch clock clk1, from the node fifo_address_read in module 2 to the node read address pin of FIFO instance has hold slack error of -1.952 ns.

It's wierd because I made clk1 and clk2 phase aligned. How can I fix this timing violation? Thank you very much.