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Altera_Forum
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14 years ago

problem on set_output_delay

Hi ,everyone: I use FPGA to send data DM642 via source-synchronous interface. DM642 uses built-in VPFE module to capture the output from FPGA. The datasheet of DM642 shows that the minimum setu...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi, jimbo:

Thank your very much for your quick reply!

However, the most thing I want to know is what kind of clock and data relation should I use; for example, center-aligned or edge-aligned? According to the parameter of the clock and data, I think choosing center-aligned is the best. Am I correct?