Forum Discussion
Altera_Forum
Honored Contributor
11 years agoWhat I think is the problem is:
In check_start, you test at rcount = 217 if RxD = 0. If so, you reset the counter and proceed to receiving. That is a half the bit time. Then you test in receiving at again at rcount=217 that's agiain at half a bit time, so that's around the signal transition of the RxD signal. You should wait a full rcount cycle to test again.