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Altera_Forum
Honored Contributor
11 years agoThe data signal can change outside the clock edge.
The datain signal becomes metastable, it is neither '1' nor '0'. You need it to be stable. You can do this very simple, by clocking it trough at least two registers. (Search the web for metastability for more info on this.) In this way your data may not be correct, but it is the same troughout the entire circuit.