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Altera_Forum
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12 years ago

problem: multiply two fractional numbers in verilog

I have to multiply two fractional numbers of 42 bits in verilog. I am using the fixed point (Q12.30). Now my result is wrong. part of my code: module my_name (out,Clk) input Clk; ...
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Altera_Forum
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11 years ago

Besides wrong result sign, how can the compiler know that you are meaning fractional numbers? Obviously the result has to be scaled by a factor of 2^12, you should also apply saturation logic to avoid overflow to wrong result when cutting 12 bits on the left.