Problem in VHDL

I would concur with FvM and tricky here.

If you're new to FPGA design and the VHDL language then basically use signals and forget about variables. You won't have to use variables at all. When you've done a bit of coding then you might start to see how regular (not shared) variables might come in useful. I've only ever used shared variables for very high levvel testbench code - forget about it for the FPGA code.

Basically you're designing digital logic. Your VHDL code is a description of that digital logic so your code should resemble the circuit: counters, adders, multiplexers etc. Sketch out what you want to produce on paper first in terms of these components. Your code should then have a direct correlation to this.

Ask yourself what bit of logic would your shared variable look like. At best it would be either: some lump of logic with lots of inputs directly driving it with no priority or a huge lump of prioritisation logic; or a load of identical lumps of logic with their outputs driving each other. I would be very very surprised if Quartus actually lets you use shard variables for synthesis - but seriously you don't need them.

Don't think of VHDL as another programming language. It isn't - it's a hardware description language. Don't think, this is how I do it in C/Java/anything else, how will VHDL let me do that. Think about logic and circuits and sketch it on paper first.

Hope this helps