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Altera_Forum
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16 years ago

Problem in VHDL

I'm trying to use variables in a LOOP to initialize all elements of a matrix, but i have a small problem. Warning (10027): Verilog HDL or VHDL warning at the main.vhd(398): index expression is ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

TYPE vetor_de_int IS ARRAY(0 TO 63) OF STD_LOGIC_VECTOR ( 0 TO 15 );

shared variable vetor: vetor_de_int;