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Altera_Forum
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8 years ago

Problem in using the same module in project for many times

Hi everyone, I am trying to use one module for several times in one project cause I want to control several ADCs using one main project. And my way to do it is like this: ADC ADC1(.RS...
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Altera_Forum
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8 years ago

Your naming is a little confusing! So DOUT1 and 2 are *inputs* to the FPGA and DIN and SCLK are *outputs* from the FPGA. DOUT1 and 2, if they are driving clock inputs, should be set up as base clocks with the create_clock command.