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Altera_Forum
Honored Contributor
15 years agoFound a workaround. Save diagram as VHDL (File->Create/Update->Create HDL from current file). Then open the VHDL file and do File->Create/Update->Create symbol files for current file.
Found a workaround. Save diagram as VHDL (File->Create/Update->Create HDL from current file). Then open the VHDL file and do File->Create/Update->Create symbol files for current file.