Forum Discussion
ARach7
New Contributor
New ContributorProblem at source files generated by Quartus from user’s “platform design” session (qsys).
Port connection width mismatches at 2 altera pcie files, “altpciexpav_stif_rx.v” and “altpciexpav_stif_tx.v”. Error-[ANALERR_SIZEMISMATCH1] Size mismatch Parameter override type mismat...
ARach7New Contributor
New Contributor1.quartus_18.1.1.646
2.PCIE
I have no more info, this issue was observed at 3rd party who tried to use VCS with Quartus.
AnandRaj_S_IntelRegular Contributor
Hi,
Check the example from below link, We can't find any Port connection width mismatches at 2 altera pcie files, “altpciexpav_stif_rx.v” and “altpciexpav_stif_tx.v”.
https://github.com/tatparya/ECE337_Project/tree/master/sourceFiles/amm_master_qsys_with_pcie/synthesis/submodules
Regards
Anand
