Problem about clock skew

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I generated a inverted clock from a dedicated clock-pin.

The statement is: assign clk_62M_inv= ~clk_62M;//clk_62M is the input clock from the dedicated clock-pin

The clock period is 16ns.

I want to constrain the time distance from clk_62M's rising edge to clk_62M_inv's rising edge to be 7.5ns-8.5ns.

How to do this?

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The question is whether clk_62M_inv is a physical output pin or not. In the case of being an output pin you will need a PLL, as kaz indicates, and preferably put that pin on one of the PLL's dedicated output pins.

If clk_62M_inv is an internal clock, you don't have to do anything, Quartus II and TimeQuest will take care of that. TimeQuest regards the the inverted clock as a 'original' clock where you also act on the falling edge. You may have to add some additional set_output_delays constraints to cope with actions on that falling edge.

Yes, clk_62M_inv is an internal clock.

I have been tried to use a PLL to generate clk_62M_inv. But there is a huge clock skew between clk_62M_inv and clk_62M. I do not know how to fix it. Would you please explain how to do this using a PLL. I want to know it.

Can I sample data on both rising edge and falling edge?

Whether I need specia constrain for this action?

Thanks.