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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem (?) using shared variables

Hi, I need your kind opinion. Please, anyone explain me why the following code is not running. VHDL code (sel-explainable) ------------------------------------------------------ en...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The problem is, you're generating a clock. You should never generate a clock. You should clock all logic with mclk. Then use clock_en to activate it: 


process(mclk)
begin
  if rising_edge(mclk) then
    if clk_en = '1' then
      --only do something when clk_en is active, say 1 in every 50
    end if;
  end if;
end process;

So this way divides your clock without having any problems associated with a generated clock.