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Altera_Forum
Honored Contributor
Honored Contributorproblem (?) using shared variables
Hi, I need your kind opinion. Please, anyone explain me why the following code is not running. VHDL code (sel-explainable)
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en...
Altera_ForumHonored Contributor
Honored ContributorThe problem is, you're generating a clock. You should never generate a clock. You should clock all logic with mclk. Then use clock_en to activate it:
process(mclk)
begin
if rising_edge(mclk) then
if clk_en = '1' then
--only do something when clk_en is active, say 1 in every 50
end if;
end if;
end process;
