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Altera_Forum
Honored Contributor
Honored Contributorproblem (?) using shared variables
Hi, I need your kind opinion. Please, anyone explain me why the following code is not running. VHDL code (sel-explainable)
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en...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This is the point, you're not supposed to generate a 50% duty cycle, as the "other" bit of code should also be using mclk as the clock. But it is only enabled with clk_en (hence it only works one in every N clocks) --- Quote End --- Sorry Tricky, my English is not so good... I didn´t understand very well this last message. Could you explain in other words, please?
