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Altera_Forum's avatar
Altera_Forum
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12 years ago

problem (?) using shared variables

Hi, I need your kind opinion. Please, anyone explain me why the following code is not running. VHDL code (sel-explainable) ------------------------------------------------------ en...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

When you say implementing, you mean with quartus? As I think I already stated, it would synthesise fine with quartus, as it just converts it to wires and will connect it up how you expect.

And you've done the conversion via std_logic_arith, which is non-standard VHDL.