Preserve inverter in BDF schematic

Following Brad,

Here's the code in VHDL to do it.

I picked up this code from somewhere in the forum (not my own)

*****

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY INVCHAIN IS

PORT (

inpin : IN STD_LOGIC;

outpin : OUT STD_LOGIC);

END INVCHAIN;

ARCHITECTURE arch OF INCHAIN IS

SIGNAL ain, bin : STD_LOGIC;

SIGNAL aout, bout : STD_LOGIC;

COMPONENT LCELL

PORT (

a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

BEGIN

ain<= NOT inpin;

LC_a : LCELL

PORT MAP (

a_in => ain,

a_out => aout);

bin<= NOT aout;

LC_b : LCELL

PORT MAP (

a_in => bin,

a_out => bout);

outpin <= bout;

end arch;