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NilsLiang_WNC's avatar
NilsLiang_WNC
Icon for New Contributor rankNew Contributor
3 years ago

Postive edge detector design

I've met a unexpected behaviour with my design and I just can't figure it out why. First, I did some logic to detect the postive edge of input signal. Then I use the pulse to drive output signal to...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Have you try to simulate the design to check the design functionality?

Does the clock toggle correctly in the signal tap?

Sharing the full design may help to further understand the problem.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.