post-synthesis simulation of a quartus design in modelsim

hey all.

i am trying use modelsim altera to perform post-synthesis simulation of my design synthesized in quartus II. These are the steps i am doing:

i) perform analysis&synthesis of my design in quartus

ii) complie the testbench(which i have written), the .vo file(generated during analysis&synthesis), and the cycloneii_atoms.v file(which is provided in the libraries) in modelsim. (i am using cyclone II device family)

iii) start simulation & selecting the testbench module for simulation.

the error comes while loading the cycloneii.v

this verilog file contains a number of modules. the error is for one of the modules and it is like this(within 'quote&unquote'):

quoting the error:

# ** Error: (vsim-3389) D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/simulation/modelsim/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (1st connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

unquoting it.

(TO EXPLAIN - testbench_MOD is the top level module in my testbench, and the testbench is testing the working of my loop_accelerator design. the "outreg_D_mux is in cycloneii.v, and is an instantiation of a mux module in cycloneii.v)

infact there are 7 such errors, and in the end it says the following &stops:

# ** Fatal: (vsim-3365) D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/simulation/modelsim/cycloneii_atoms.v(5764): Too many port connections. Expected 4, found 11.

can anyone help me understand what is going on exactly?

thanks,

-anu