Can you tell me why post-fit (quartus_fit) mismatches the post-synthesis (quartus_map) simulation? I had a design with counter. A test bench waits for CLK to release the reset. This works in post-synthesis. But a delay after clock edge is needed to reset the post-fit counter. How is it possible?

Here is an example. The synthesized counter first library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity BIST is port ( clk, start: std_logic; CNT: buffer integer range 0 to 1000 ); end BIST; architecture RTL of BIST is begin FF: process (CLK) begin if Rising_Edge(Clk) then if CNT = 1000 then CNT <= 0; else CNT <= CNT+1; end if; if START='1' then CNT <= 0; end if; end if; end process; end RTL; and the verification test bench: library IEEE, POST_SYNth_CUT; use IEEE.STD_LOGIC_1164.ALL; entity VERIF_TB is end VERIF_TB ; architecture BEH of VERIF_TB is signal CLK: std_logic; constant PERIOD: TIME := 10 ns; signal START: std_logic; begin FUNC: entity WORK.BIST port map( CLK => CLK, START => START, CNT => open ); PS: entity post_synth_CUT.BIST port map( CLK => CLK, START => START, CNT => open ); CLOCK : process begin CLK <= '0'; wait for 85*PERIOD/100; CLK <= '1'; wait for 15*PERIOD/100; end process; START_PROC: process begin START <= '0'; for cycle_cnt in 0 to 20 loop wait until CLK = '1'; end loop; -- wait for 1 fs; -- add a delta dealy START <= '1'; -- pulse start wait until CLK = '1'; START <= '0'; wait; end process; end BEH; On the 21th count (clock period), the start is made high. On the next clock, count is zero, therefore. But, it is not in the post-fit simulation. The post-fit becomes 20->0 instead of taking value 21 as expected and as RTL and post-synthesis do. It seems that post-fit process, on clock edge, takes the start <= '1' that is raised after clock. It does not appear correct. If TB delays the start by a moment then both counters are synchronous. Is it because I use "9.1 Build 222 10/21/2009 SJ Web Edition" or Stratix II EP2S15F484C3? Simulator goes crazy?

I think, setting CLK and other input signals simultaneously doesn't create a valid timing, neither for a real device nor in simulation. It's normal behaviour to get differences in simulation behaviour in case of timing violations. Unless intended to reveal existing timing problems, test benches should use a robust, unequivocal timing in my opinion.

--- Quote Start --- ModelSim or Quartus Simulator? --- Quote End --- It is ActiveHDL 7.2. But, I do nor remeber if I had any problems with either Xilinx or functional simulation. if I define the small range counter CNT: buffer integer range 0 to 1 the post-fit will not even compile because of # Compile Error: Explicit type conversions are allowed between closely related types only.at line CNT <= IEEE.STD_LOGIC_ARITH.CONV_INTEGER(SIGNED(ww_CNT));Range 0..2, CNT: buffer integer range 0 to 2compiles but crushes in simulation RUNTIME Fatal Error: Value -2 out of range (0 to 2). on the same line. Even the initial value CNT: buffer integer range 0 to 2:= 0does not change the things. Where the negatives comes from? Either I do not understand something or there are more problems with Altera fitter than those related to delta delay. The RTL and post-synth still run somoothly. --- Quote Start --- setting CLK and other input signals simultaneously doesn't create a valid timing --- Quote End --- Where do you see them changed simultaneously?

--- Quote Start --- ModelSim or Quartus Simulator? --- Quote End --- ModelSim is in conspiracy with Active-HDL -- they show absolutely the identical results: boht the delta-delay and negative values appearing in post-fit! And, latest, SP2, WebEdition of Quartus is not better.

'Post-map' matches 'rtl functional' but differs from 'post-fit'

14 Replies

Altera_Forum
Honored Contributor
15 years ago
Do you mean that post-fit includes the timing infromation, despite of the "Functional Simulation Only" option in netlist writer?
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Do you mean that post-fit includes the timing infromation, despite of the "Functional Simulation Only" option in netlist writer?
--- Quote End ---

Most likely not if explicitely set. I asked, because functional simulation of post-fit netlist seems unusual to me. I only used it for timing analysis. The question is however, which difference in the netlist can change execution sequence in functional simulation?.
Altera_Forum
Honored Contributor
15 years ago
Have you tried doing this again without using the buffer port type? Its hardly used by anyone, and not really the standard way to create output registers. Usually you would use an internal signal to store the value and assign an output to the internal signal. Another thing I notice is that in your code you have 2 separate if statements resetting the counter. It would be more common to use something like:

if CNT= 1000 or START = '1' then CNT <= 0; else CNT <= CNT + 1; end if;
Altera_Forum
Honored Contributor
15 years ago
@Tricky: I don't see, why the said constructs, that are legal and well-defined VHDL code, should change the synthesis result.

Regarding negative integers, I understood a bit more when reviewing your post. The integer signal has to be converted to a numerical bit-vector during synthesis. One should expect integer range 0 to 1000 to be converted to unsigned(9 downto 0). Quartus generally accepts integer signals, also for ports, and generates correct code for it. They are even suggested in the Quartus language templates. But in the said case, Quartus converts the integer apparently to a signed signal:
CNT <= IEEE.STD_LOGIC_ARITH.CONV_INTEGER(SIGNED(ww_CNT));

That's no problem in logic synthesis, because the bit-vector is identical. But the simulator stumbles upon it. It may be necessary to change to an unsigned port signal for simulation of Quartus post-fit netlists.

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'Post-map' matches 'rtl functional' but differs from 'post-fit'

14 Replies

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