'Post-map' matches 'rtl functional' but differs from 'post-fit'

@Tricky: I don't see, why the said constructs, that are legal and well-defined VHDL code, should change the synthesis result.

Regarding negative integers, I understood a bit more when reviewing your post. The integer signal has to be converted to a numerical bit-vector during synthesis. One should expect integer range 0 to 1000 to be converted to unsigned(9 downto 0). Quartus generally accepts integer signals, also for ports, and generates correct code for it. They are even suggested in the Quartus language templates. But in the said case, Quartus converts the integer apparently to a signed signal:

CNT <= IEEE.STD_LOGIC_ARITH.CONV_INTEGER(SIGNED(ww_CNT));

That's no problem in logic synthesis, because the bit-vector is identical. But the simulator stumbles upon it. It may be necessary to change to an unsigned port signal for simulation of Quartus post-fit netlists.