possible constraint problem (source sync input to fpga)

Hello,

I had thought I had my source synchronous input properly constrained, but I recently added some logic to another part of my design (signaltap, and some other stuff), and now I sometimes see errors on the data received by the FPGA on a source synchronous interface, center aligned clock (GMII). The GMII interface is specified with a Thold and Tsetup relative to the clock from the phy.

Clk: 8ns, Th = 1nS, Tsu = 2.5nS (see attached image)

My constraints for the interface are as follows:

create_clock -name {phy_rxclk} -period 8.000 -waveform { 4.000 8.000 } [get_ports {phy_rxclk}]

create_clock -name {phy_rxclk_vir} -period 8.000

set phy_period 8

set phy_tsu 2.5

set phy_th 1

set phy_indelay_max [expr $phy_period/2 -$phy_tsu]

set phy_indelay_min [expr $phy_th - $phy_period/2]

set_input_delay -max $phy_indelay_max -clock {phy_rxclk_vir} [get_ports phy_rxd*]

set_input_delay -min $phy_indelay_min -clock {phy_rxclk_vir} [get_ports phy_rxd*]

I also had assigned the receive register as Fast Input Registers. I'm currently not using a PLL on the receive clock. Can someone tell me if I've specified the constraints incorrectly? Quartus was placing the phy_rxclk on the global clock lines, but I've been trying things like assigning it to a regional clock in order to eliminate skew.

Thanks.