@posedge vs @negedge

I'm looking over some demo code, trying to teach myself Verilog. At one place I see:

always@(posedge CLK)

and elsewhere I find:

assign CLK_n = ~CLK;

always@(negedge CLK_n)

It would seem to me that the later is an oddly complicated way to say the same as the former. I assume I'm missing something here and there's an excellent reason for doing it this way. Can someone enlighten me?