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Altera_Forum
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14 years ago

@posedge vs @negedge

I'm looking over some demo code, trying to teach myself Verilog. At one place I see: always@(posedge CLK) and elsewhere I find: assign CLK_n = ~CLK; always@(negedge CLK_n) It ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Yes I may not have chosen the best example, trying to oversimplify it. As for the fact that there is no glitch when only one LUT input changes, it is indeed a generally accepted fact but I'm not sure it was ever said officially by Altera. IIRC only Xilinx told that, so I prefer not relying on it.