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Hello Kaz..
I believe in the second case, an explicit inverter gate will get placed after the clock source to generate the inverted clock? And this, depending on the frequency of the clock and the propagation delay through the gate could be a problem right?
But I do not see a reason why should it be good for ASICs as well. Perhaps if you could enlighten us as to what makes it bad design for FPGAs and will do for ASICs it would be great ..
Keen to hear from you
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ASIC designers decide their own cells and routing, to them gating clock is "usual" practice. FPGAs have prefabricated dense routing and this means clock signal could get delayed in the routing mess. The remedy is that fpgas have their clock routing separate from anything else.
By the way many many ASIC engineers are losing their jobs and moving to fpga jobs but unfortunately there is some bias, they think fpga case is subset of the asic superset hence they join excited only to face serious difficulties.
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