@posedge vs @negedge

I generally agree about the glitch problems of LUT. In the special case, I'm not clear which specific FPGA family your example is referring to. The two LUT outputs scenario seems to apply to Stratix family. There LUT's are comprised of smaller 3 and 4 input blocks internally and there's no reason to assume, that input signals assigned to different inputs are interacting in the said way. As far as I remember, it's generally expecting that LUTs don't generate glitches with a single input changing.

It's also suggested to take a look at the real device hardware when discussing about clock inversion. Doing so reveals, that inversion of control signals, e.g. clocks, is a LAB-wide feature with all Altera FPGA families. Unless you are using constructs like gated clocks or clock dividers, LUTs never come in touch with the clock path.