@posedge vs @negedge

In the latter case the two inverters will probably be optimized away anyway so we come back to the first set up. I agree it's just a more complicated way of saying the same thing.

Now for the combinatorial clock problem: the main problem is that FPGAs don't use gates, but look up tables. When you do an inverter, inside the FPGA you will use one input and one output from one LUT to perform the function. The rest of the LUT isn't used, but for optimization reasons, the mapper/fitter may decide to add another logic function in the same LUT, using other inputs and outputs.

Lets say the LUT is now used to do two inverters. The LUT's truth table is rather simple:

A|B||X|Y
-+-++-+-
0|0||1|1
0|1||1|0
1|0||0|1
1|1||0|0

Now lets say A is your clock signal, and B is something different. If B changes, then X, the inverted A, is supposed to stay the same. But in practise, as you are switching the LUT from one state to the other, during the transition all the LUT outputs can temporarily take any value, before the LUT stabilizes to it's new state. This isn't a problem with regular registers, as those glitches happen outside clock edges. But for a clock signal, if you have a glitch on the X output after a change on B, this glitch could be seen as a clock edge for some registers, causing lots of trouble in the design.

You don't have this problem with ASICs because when you want to invert a signal... you use an inverter ;)