Forum Discussion
Occasional ContributorPorting from Xilinx to Altera
I believe I have provided the support/answer that you needed in order to proceed with your project. With that, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
Super ContributorWe have an internal tool that will help to convert the design using UltraScale and UltraScale+ to our Agilex device.
There is limitations for other Xilinx devices: example some primitives are not supported.
Also, the Xilinx project files will not added to the Intel project:
- The Xilinx Vivado generated files (including IPs, Xilinx templates, or any other files that are under Xilinx license)
- The constraints
- Block Design files
Plus you have 44 ip cores of Xilinx, all of it will be black box.
If you want me to convert the design, you will need to provide me the .xpr project files. Once converted, I will send you back the .qpf files and you can start work on your design.
To define a parameter outside the module of a HDL, the Quartus software allows you to assign global, project-wide default values for parameters on the Default Parameter Settings page in the Settings dialog box. You may checkout this.
https://www.doulos.com/knowhow/fpga/settings-genericsparameters-for-synthesis/
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
