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"I think that you'll find embracing the new tools can be just as quick and efficient as using your old ones "
Okay, lets give this a try. please point me to a link that will walk me trough modelsimAltera, and , give me 15 years of working knowledge in 30 min or less..
I am half way serious here, please point me to some link that will get me through chip-trip using model-sim.
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Well, this is more or less how I work. Note, I only use Verilog/VHDL.
I don't use AHDL or schematics.
Quartus has a "Native Link" option to automatically call ModelSim.
However, I prefer to run ModelSim manually, because it's stupid to launch ModelSim every time I make a change.
1. Create the project folder (ie, "my_project"). This is where the source code and Quartus file will reside.
2. Under "my_project", create the "simulation/modelsim". This is where ModelSim's files will reside and, more importantly, is where
3. Start ModelSim and create a new project in "my_project/simulatiion/modelsim/" called whatever.
4. Using your favourite editor, create the files
- my_project/my_project.v
- my_project/my_project_tb.v
- my_project/simulation/modelsim/run_rtl.do
- my_project/simulation/modelsim/run_gate.do
5. In ModelSim, add these files to the project
6. In ModelSim, execute the run_rtl.do file *voila*, it's simulating.
You don't need to go through this process everytime you make a change to one of the .v files.
You can just recompile the file in ModelSim, restart the simulation and run it again.
When you're happy, time to move on to Quartus and gate level simulation
1. Start Quartus and create a new project in "my_project" and add the "my_project.v" file.
2. In Quartus, go to Settings -> Simulation. Make sure the EDA NetList writer is on, it's aimed at simulation/modelsim and the output is set to Verilog.
3. In Quartus, compile the project. It will dump a series of gate level Verilog models in simulation/modelsim.
4. Start ModelSim.
5. In ModelSim, execute the run_gate.do file
To simulate different models, select the appropriate "my_project_xxx_vo" file.
A few important differences between run_rtl.do and run_gate.do:
run_rtl.do compiles everything into a library called "work" and loads just the generic Altera Verilog libraries.
run_gate.do does not compile the original RTL code, only the gate level model generated by Quartus. It compiles everything into a library called "gate_work" and, besides Altera's libraries, loads the Cyclone IV libraries.
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