pll output frequency

I am getting 6.25khz clock output from a 40mhz clock input after pll(cyclone4-150)

I shoud be getting 40mhz.

1-What can be gone wrong?

2-To debug I just want to connect an output directly to a clock without using pll but I get error. Why do I get routing error if I want do connect an output directly a lvds_input_clock_p on the top vhdl block? To connect a regular IO to an input p pin of an input(lvds clock0)

--Do I need to write both p and n on the top vhdl block and connect p

--Do I need to instantiate lvdsio buffer on the top?