PLL output clk maximum frequency at 3.3LVCMOS

I'm trying to output a 80MHz clock from a pll to a SDRAM. Quartus complains with the following

Critical Warning: Output pin "MEM_CLK" (external output clock of PLL "pll_80:e1|altpll:altpll_component|pll_80_altpll1:auto_generated|pll1") uses I/O standard 3.3-V LVCMOS, has current strength 2mA, output load 0pF, and output clock frequency of 80 MHz, but target device can support only maximum output clock frequency of 64 MHz for this combination of I/O standard, current strength and load

When I play around with the current strength I get only min,max, and 2 mA. From what I can tell 2mA is the max. So, is there something I'm missing or is there really this limit on output clocks at the 3.3LVCMOS standard. The signal looks to be right at 80 MHz when I look at it with a scope, so can I just ignore this warning or am I doing something wrong?