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Altera_Forum's avatar
Altera_Forum
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12 years ago

PLL not working in Modelsim

Hello,

I'm using Quartus 12.1. I created a SOPC system, and now I'm trying to simulate it. In the SOPC builder I get a warning message : "altpll_0: The module properties SIMULATION_MODEL_IN_VERILOG and SIMULATION_MODEL_IN_VHDL can not both be set when using the simulation file property: C:\path/altpll_0.vhd.

In modelsim, the clocks generated by the PLL are undefined.

I have done this several times in version 10.1, but with 12.1 there seems to be something different. Does anybody know how to fix this issue.

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    If you couldn't find a solution by now, you can try to search all project files for "SIMULATION_MODEL_IN_VERILOG" and remove it.

    Are you simulating with a Tcl script or with a Modelsim Project (.mpf or so)?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    This is a niosII project. I used the SOPC. I'm working in vhdl. The sopc system creates a testbench, I'm using this testbench to simulate the system in ModelSim. This process used to work just fine in 10.1.